Field of the Invention
The invention relates to a device and to a method for encoding a stream of data bits of binary source signal into a stream of data bits of a binary channel signal, wherein the bit stream of the source signal is divided into n-bit source words, which device includes converting means adapted to convert the source words into corresponding m-bit channel words.
An encoding device mentioned in the foregoing is known from the book xe2x80x98Coding techniques for digital recordersxe2x80x99 by K. A. Schouhamer Immink, chapter 5,6,7, pp. 127 to 131, Prentice Hall (1991). The book discusses an encoder for generating a (d,k) sequence which satisfies the parameters: rate 2/3, (1.7), which encoder is also proposed by Cohn et al in U.S. Pat. No. 4,337,458. The known encoding scheme suffers from the presence of a DC level which may become excessively large and therefore introduces distortion in communication systems which cannot handle a DC component, as well as distortion in any recording of data in magnetic media.
The invention has for its object to provide a device for encoding n-bit source words into corresponding m-bit channel words in, such a manner that the device itself does not generate a DC component in the channel signal, whereas further it provides the possibility, by means of additional measures to be taken, also provides a possibility of realizing a channel signal in the form of a (d,k) sequence.
The device in accordance with the invention is characterized in that each value of the n-bit source words together with another value of the n-bit source words forms a pair of source words, the values of the source words of said pair of n-bit source words differ in the bit value of the qth bits in the n-bit source words, q being a constant, the pairs of n-bit source words being subdivided into a first part and a remaining part, and the converting means are adapted to convert n-bit source words into m-bit channel words, in such a manner that the conversion of the two source words forming a pair of source words of the first part of the pairs of n-bit source words is parity preserving and the conversion of the two source words forming a pair of source words of the remaining part of the pairs of n-bit source words is parity inverting.
xe2x80x98Parity preservingxe2x80x99 means that the parity of the n-bit source words to be converted is the same as the parity (after modulo-2 addition) of the corresponding m-bit channel words into which they are converted. xe2x80x98Parity invertingxe2x80x99 means that the parity of the n-bit source words to be converted is the inverse of the parity (after modulo-2 addition) of the corresponding m-bit channel words into which they are converted. As a result, a unique relationship between the parity of the two source words of a pair and the parity of the corresponding channel words can be obtained, enabling an efficient DC control for the binary channel signal, after aT precoding.
The encoding device in accordance with the invention can be used in combination with a bit-adder unit in which one bit is added to code words of a certain length. The signal obtained can be applied to the encoding device of the present invention. The channel signal of the encoding device is applied to a 1T-precoder. The purpose of the bit-adder unit is to add a xe2x80x980xe2x80x99 bit or a xe2x80x981xe2x80x99 bit to blocks of data in the input signal of the converter, so as to obtain a precoder output signal which is DC free or which includes a tracking pilot signal having a certain frequency. The precoder output signal is recorded on a record carrier. The addition of the one bit to the code words of a certain length is such that this bit will be on the qth bit position of the n-bit source words to be supplied to the converter. In this way two different n-bit source words may be obtained. The n-bit source words thus obtained differ only in the value of the bit in the qth bit position. These two n-bit source words form the pair of n-bit source words. In the case that the conversion of said pair of source words is parity preserving, the addition of a xe2x80x980xe2x80x99 bit to the input signal of the converter results in the polarity remaining the same in the output signal of the 1T precoder and the addition of a xe2x80x981xe2x80x99 bit results in a polarity inversion in the output signal of the 1T precoder. In the case that the conversion of said pair of source words is parity inverting, the addition of a xe2x80x980xe2x80x99 bit in the input signal of the converter results in polarity inversion in the output signal of the 1T precoder and the addition of a xe2x80x981xe2x80x99 bit results in the polarity of the output signal of the 1T precoder remaining the same. The converter therefore influences the output signal of the 1T precoder in such a manner that the running digital sum value of the output signal of the 1T precoder can be controlled so as to have a desired pattern as a function of time.
Preferably, the device in accordance to the invention is characterized in that the converting means are adapted to convert a block of p consecutive n-bit source words into a corresponding block of p consecutive m-bit channel words, where n, m and p are integers, m greater than nxe2x89xa72, pxe2x89xa71, and where p may vary.
Preferably, m equals n+1, and n is equal to 2. When n is 2, the device in accordance with the invention, in conjunction with additional measures to be taken, as will become apparent later, can be used ng channel signals in the form of a (d,k) sequence, where d=1. Higher values for n do not allow the generation of a (1,k) sequence. Further, n=2, which means that 2-bit source words are converted into 3-bit channel words, results in a 50% increase in bits in the channel signal generated by the device.
Various conversions of 2-bit source words into 3-bit channel words are possible in which pairs of n-bit source words are parity preserving or parity inverting. It should, however, be noted that various permutations of the channel codes in the Table are possible, namely 8 in total.
The device in accordance with the invention wherein the converting means are adapted to convert 2-bit source words into corresponding 3-bit channel words, so as to obtain a channel signal in the form of a (d,k) sequence, where d=1, the device further comprising means for detecting the position in the bit stream of the source signal where encoding of single 2-bit source words into corresponding single channel words would lead to a violation of the d-constraint at the channel word boundaries and for supplying a control signal in response to said detection, may be further characterized in that, in the absence of the control signal, the converting means are adapted to convert single 2-bit source words into corresponding single 3-bit channel words.
More specifically, the device is characterized in that, in the presence of said control signal, the converting means are further adapted to convert the block of said two subsequent 2-bit source words into a corresponding block of two subsequent 3-bit channel words.
The measure to convert one (say: the second one) of two subsequent source words into a 3-bit word not identical to the four channel words CW1 to CW4, offers the possibility of detecting at the receiver side that a situation existed in which encoding of single source words into corresponding single channel words would have led to a violation of the d=1 constraint. The encoder now encodes a block of two 2-bit source words into a block of two 3-bit channel words. Each value of the block of two 2-bit source words together with another value of the block forms a pair of two 2-bit source words, where the values of said pair of two 2-bit source words differ in the bit value of the qth bit in one of the two 2-bits source words. In this way, the converter influences the output of the 1T precoder in such a manner that the running digital value of the output signal of the 1T precoder can be controlled so as to have a desired pattern as a function of time, while the d=1 constraint is satisfied as well.
To encode blocks of two 2-bit source words, the device in accordance with the invention may be characterized in that the converting means are adapted to convert the blocks of two consecutive 2-bit source words into the blocks of two consecutive 3-bit channel words in accordance with the coding given in the following Table:
The device in accordance with the invention, for generating a (d,k) sequence, wherein k has a value larger than 5, the device being further having means for detecting the position in the bit stream of the source signal where encoding of single 2-bit source words into single 3-bit channel words would lead to a violation of the k-constraint and for supplying a second control signal in response to said detection, may be further characterized in that, in the presence of the second control signal, which occurs during the conversion of three consecutive 2-bit source words, the converting means are adapted to convert a block of said three consecutive 2-bit source words into a block of three corresponding consecutive 3-bit channel words, the converting means are further adapted to convert two of the three source words in the block into corresponding 3-bit channel words not identical to the four channel words CW1 to CW4, in order to preserve the k constraint.
This measure enables an encoding of a block of three 2-bit source words into a block of three 3-bit channel words so as to satisfy the k-constraint, and in such a manner that the encoding is still so as to allow the running digital sum value of the 1T precoder to be controlled so as to have a desired pattern as a function of time.
The measure to convert two (say: the second and the third one) of three subsequent source words into a 3-bit word not identical to the four channel words CW1 to CW4, offers the possibility of detecting at the receiver end that a situation existed in which encoding of single 2-bit source words into corresponding single 3-bit channel words would have led to a violation of the k constraint. Upon detection, the decoder is capable of decoding the block of three 3-bit channel words into the corresponding block of three 2-bit source words a way inverse to that during encoding.
To encode blocks of three 2-bit source words, the device in accordance with the invention may be characterized in that the converting means are adapted to convert blocks of three consecutive 2-bit source words into blocks of three consecutive 3-bit channel words in accordance with the coding given in the following Table:
A device for decoding a stream of data bits of a binary channel signal into a stream of data bits of a binary source signal, wherein the bit stream of the channel signal is divided into m-bit channel words, which device comprises deconverting means adapted to deconvert m-bit channel words into corresponding n-bit source words, is characterized in that each value of the n-bit source words together with another value of the n-bit source words forms a pair of source words, the values of the source words of said pair of n-bit source words differ in the bit value of a qth bits in the n-bit source words, q being a constant, the pairs of n-bit source words being subdivided into a first part and a remaining part, and the deconverting means are adapted to deconvert m-bit channel words into n-bit source words, in such a manner that the deconversion of the m-bit channel words into the source words that form a pair of source words of the first part of the pairs of n-bit source words is parity preserving and the deconversion of the m-bit channel words into the source words that form a pair of source words of the remaining part of the pairs of n-bit source words is parity inverting.
It should be noted that U.S. Pat. No. 4,547,890 discloses a converter for converting n-bit source words into m-bit channel words, which channel signal is DC free. The converter, however, does not in all situations convert n-bit source words into m-bit channel words, in such a manner that the conversion of the two source words forming a pair of source words of the first part of the pairs of n-bit source words is parity preserving and the conversion of the two source words forming a pair of source words of the remaining part of the pairs of n-bit source words is parity inverting. Furthermore, an algorithm is necessary to select an m-bit channel word so as to produce a DC free output.